Miodrag Milanović b20df72e1e Merge pull request #4536 from YosysHQ/functional ... Functional Backend		2024-09-06 10:05:04 +02:00
..
aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
arch	add min_ce_use and min_srst_use parameters	2024-08-15 17:50:36 +02:00
asicworld
bind	Add support for parsing the SystemVerilog 'bind' construct	2021-07-16 09:31:39 -04:00
blif
bram
cxxrtl	cxxxrtl: fix use of format specifiers in test	2024-06-11 07:22:39 +01:00
errors
fmt
fsm
functional	functional tests: run from make tests but not smtlib/rkt tests	2024-09-04 10:30:08 +01:00
hana
liberty	Extend liberty tests	2024-08-13 18:47:36 +02:00
lut
memfile
memlib	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
memories	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
opt	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
opt_share
proc	proc_dff: add tests	2024-08-28 16:24:47 +01:00
realmath
rpc
sat
select
share
sim
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap	cellmatch: Rename the special design to $cellmatch	2024-05-03 16:42:41 +02:00
tools
unit
various	Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting	2024-08-21 14:28:42 +01:00
verific
verilog
vloghtb
xprop
gen-tests-makefile.sh