abc9_dff.ys
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Fix tests for check in equiv_opt
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2022-10-07 16:04:51 +02:00 |
asym_ram_sdp.ys
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Asymmetric port ram tests with Xilinx
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2023-02-21 05:23:14 +13:00 |
attributes_test.ys
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
blockram.ys
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
bug3670.v
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ABC9: Cell Port Bug Patch (#3670)
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2023-04-22 16:24:36 -07:00 |
bug3670.ys
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ABC9: Cell Port Bug Patch (#3670)
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2023-04-22 16:24:36 -07:00 |
dsp_abc9.ys
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Add ABC9 DSP cascade test
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2023-05-25 18:42:08 +01:00 |
dsp_fastfir.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
fsm.ys
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FfData: some refactoring.
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2021-10-07 04:24:06 +02:00 |
lutram.ys
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
mux_lut4.ys
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Update tests
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2023-06-09 14:41:45 +02:00 |
opt_lut_ins.ys
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Fix tests for check in equiv_opt
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2022-10-07 16:04:51 +02:00 |
priority_memory.v
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Tests for ram_style = "huge"
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2023-02-21 05:23:15 +13:00 |
priority_memory.ys
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Tests for ram_style = "huge"
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2023-02-21 05:23:15 +13:00 |
xilinx_dffopt.ys
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Fix tests for check in equiv_opt
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2022-10-07 16:04:51 +02:00 |