yosys/tests/proc/rmdead.ys at c016f6a4236fb970196f35c2afb0f2c7c237a77f - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-05 17:14:08 +00:00

Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards

If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.

2021-07-29 20:55:59 -04:00

5 lines

67 B

Plaintext

Raw Blame History

 read_verilog rmdead.v
 proc
 opt_clean
 select -assert-count 0 w:fail