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c016f6a423
If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
47 lines
948 B
Verilog
47 lines
948 B
Verilog
module top (
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input wire signed x,
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output reg [31:0] y
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);
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wire signed fail = ~x;
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always @*
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case (x)
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1'b0: y = 0;
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1'b1: y = 1;
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default: y = fail;
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endcase
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always @*
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case (x)
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2'sb00: y = 0;
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2'sb00: y = fail;
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endcase
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always @*
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case (x)
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2'sb00: y = 0;
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default: y = fail;
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2'sb01: y = 1;
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2'sb10: y = 2;
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2'sb11: y = 3;
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2'sb00: y = fail;
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2'sb01: y = fail;
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2'sb10: y = fail;
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2'sb11: y = fail;
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endcase
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always @*
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case ({x, x})
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2'b00: y = 0;
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2'b01: y = 1;
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2'b10: y = 2;
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2'b11: y = 3;
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default: y = fail;
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2'b00: y = fail;
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2'b01: y = fail;
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2'b10: y = fail;
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2'b11: y = fail;
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endcase
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endmodule
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