mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-28 19:01:30 +00:00
b98376884e
These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine. |
||
|---|---|---|
| .. | ||
| aiger | ||
| arch | ||
| asicworld | ||
| bind | ||
| blif | ||
| bram | ||
| errors | ||
| fsm | ||
| hana | ||
| liberty | ||
| lut | ||
| memfile | ||
| memories | ||
| opt | ||
| opt_share | ||
| proc | ||
| realmath | ||
| rpc | ||
| sat | ||
| select | ||
| share | ||
| simple | ||
| simple_abc9 | ||
| smv | ||
| sva | ||
| svinterfaces | ||
| svtypes | ||
| techmap | ||
| tools | ||
| unit | ||
| various | ||
| verilog | ||
| vloghtb | ||
| gen-tests-makefile.sh | ||