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18 lines
352 B
Verilog
18 lines
352 B
Verilog
// Demo for $anyconst
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module demo5 (input clk);
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wire [7:0] step_size = $anyconst;
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reg [7:0] state = 0, count = 0;
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reg [31:0] hash = 0;
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always @(posedge clk) begin
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count <= count + 1;
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hash <= ((hash << 5) + hash) ^ state;
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state <= state + step_size;
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end
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always @* begin
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if (count == 42)
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assert(hash == 32'h A18FAC0A);
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end
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endmodule
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