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https://github.com/YosysHQ/yosys
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248 lines
7.3 KiB
Verilog
248 lines
7.3 KiB
Verilog
`default_nettype none
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module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sp
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module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk, write_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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data_out_r <= memory[address_in_r];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp
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module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // wd=16, wa=9
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(
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input wire clk_w, clk_r, write_enable,
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input wire [WORD-1:0] data_in,
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input wire [ADDRESS_WIDTH_W-1:0] address_in_w,
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input wire [ADDRESS_WIDTH-1:0] address_in_r,
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output wire [DATA_WIDTH-1:0] data_out
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);
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localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-SHIFT_VAL;
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localparam BYTE = DATA_WIDTH;
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localparam WORD = DATA_WIDTH<<SHIFT_VAL;
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localparam DEPTH = 2**ADDRESS_WIDTH_W;
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localparam SUB_DEPTH = 2**SHIFT_VAL;
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reg [BYTE-1:0] data_out_r;
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reg [BYTE-1:0] memory [0:DEPTH-1];
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integer i;
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always @(posedge clk_w) begin
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for (i=0; i<SUB_DEPTH; i=i+1)
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if (write_enable)
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memory[{address_in_w, i}] <= data_in[i*BYTE+:BYTE];
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end
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always @(posedge clk_r) begin
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data_out_r <= memory[address_in_r];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp_wwr
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module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // rd=16, ra=9
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(
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input wire clk_w, clk_r, write_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in_w,
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input wire [ADDRESS_WIDTH_R-1:0] address_in_r,
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output wire [WORD-1:0] data_out
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);
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localparam ADDRESS_WIDTH_R = ADDRESS_WIDTH-SHIFT_VAL;
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localparam BYTE = DATA_WIDTH;
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localparam WORD = BYTE<<SHIFT_VAL;
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localparam DEPTH = 2**ADDRESS_WIDTH;
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localparam SUB_DEPTH = 2**SHIFT_VAL;
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reg [WORD-1:0] data_out_r;
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reg [BYTE-1:0] memory [0:DEPTH-1];
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always @(posedge clk_w) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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end
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integer i;
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always @(posedge clk_r) begin
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for (i=0; i<SUB_DEPTH; i=i+1)
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data_out_r[i*BYTE+:BYTE] <= memory[{address_in_r, i}];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp_wrr
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module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10)
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(
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input wire write_enable_a, clk_a,
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input wire [DATA_WIDTH_A-1:0] data_in_a,
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input wire [ADDRESS_WIDTH_A-1:0] address_in_r_a, address_in_w_a,
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output wire [DATA_WIDTH_A-1:0] data_out_a,
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input wire write_enable_b, clk_b,
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input wire [DATA_WIDTH_B-1:0] data_in_b,
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input wire [ADDRESS_WIDTH_B-1:0] address_in_r_b, address_in_w_b,
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output wire [DATA_WIDTH_B-1:0] data_out_b
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);
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sync_ram_sdp #(
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.DATA_WIDTH(DATA_WIDTH_A),
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.ADDRESS_WIDTH(ADDRESS_WIDTH_A)
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) a_ram (
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.write_enable(write_enable_a),
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.clk(clk_a),
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.data_in(data_in_a),
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.address_in_r(address_in_r_a),
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.address_in_w(address_in_w_a),
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.data_out(data_out_a)
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);
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sync_ram_sdp #(
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.DATA_WIDTH(DATA_WIDTH_B),
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.ADDRESS_WIDTH(ADDRESS_WIDTH_B)
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) b_ram (
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.write_enable(write_enable_b),
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.clk(clk_b),
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.data_in(data_in_b),
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.address_in_r(address_in_r_b),
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.address_in_w(address_in_w_b),
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.data_out(data_out_b)
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);
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endmodule // double_sync_ram_sdp
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module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk_a, clk_b,
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input wire write_enable_a, write_enable_b,
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input wire read_enable_a, read_enable_b,
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input wire [DATA_WIDTH-1:0] write_data_a, write_data_b,
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input wire [ADDRESS_WIDTH-1:0] addr_a, addr_b,
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output reg [DATA_WIDTH-1:0] read_data_a, read_data_b);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] mem [0:DEPTH];
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always @(posedge clk_a) begin
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if (write_enable_a)
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mem[addr_a] <= write_data_a;
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else
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read_data_a <= mem[addr_a];
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end
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always @(posedge clk_b) begin
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if (write_enable_b)
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mem[addr_b] <= write_data_b;
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else
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read_data_b <= mem[addr_b];
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end
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endmodule // sync_ram_tdp
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module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(
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input wire clk_a_0,
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input wire write_enable_a_0, read_enable_a_0,
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input wire [DATA_WIDTH-1:0] write_data_a_0,
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input wire [ADDRESS_WIDTH-1:0] addr_a_0,
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output wire [DATA_WIDTH-1:0] read_data_a_0,
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input wire clk_a_1,
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input wire write_enable_a_1, read_enable_a_1,
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input wire [DATA_WIDTH-1:0] write_data_a_1,
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input wire [ADDRESS_WIDTH-1:0] addr_a_1,
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output wire [DATA_WIDTH-1:0] read_data_a_1,
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input wire clk_b_0,
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input wire write_enable_b_0, read_enable_b_0,
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input wire [DATA_WIDTH-1:0] write_data_b_0,
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input wire [ADDRESS_WIDTH-1:0] addr_b_0,
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output wire [DATA_WIDTH-1:0] read_data_b_0,
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input wire clk_b_1,
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input wire write_enable_b_1, read_enable_b_1,
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input wire [DATA_WIDTH-1:0] write_data_b_1,
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input wire [ADDRESS_WIDTH-1:0] addr_b_1,
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output wire [DATA_WIDTH-1:0] read_data_b_1
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);
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sync_ram_tdp #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) ram_0 (
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.clk_a(clk_a_0),
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.clk_b(clk_b_0),
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.write_enable_a(write_enable_a_0),
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.write_enable_b(write_enable_b_0),
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.read_enable_a(read_enable_a_0),
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.read_enable_b(read_enable_b_0),
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.write_data_a(write_data_a_0),
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.write_data_b(write_data_b_0),
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.addr_a(addr_a_0),
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.addr_b(addr_b_0),
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.read_data_a(read_data_a_0),
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.read_data_b(read_data_b_0)
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);
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sync_ram_tdp #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) ram_1 (
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.clk_a(clk_a_1),
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.clk_b(clk_b_1),
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.write_enable_a(write_enable_a_1),
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.write_enable_b(write_enable_b_1),
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.read_enable_a(read_enable_a_1),
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.read_enable_b(read_enable_b_1),
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.write_data_a(write_data_a_1),
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.write_data_b(write_data_b_1),
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.addr_a(addr_a_1),
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.addr_b(addr_b_1),
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.read_data_a(read_data_a_1),
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.read_data_b(read_data_b_1)
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);
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endmodule // double_sync_ram_tdp
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