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73cf658996
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate RTLIL that exclusively reference a signed wire. - AST_CONCAT may also contain a memory write.
45 lines
1,008 B
Verilog
45 lines
1,008 B
Verilog
`define OUTPUTS(mode) \
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o``mode``0, \
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o``mode``1, \
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o``mode``2, \
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o``mode``3, \
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o``mode``4
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module gate(
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input [1:0] iu,
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input signed [1:0] is,
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output [2:0] `OUTPUTS(u),
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output signed [2:0] `OUTPUTS(s)
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);
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`define INSTANCES(mode) \
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mod m``mode``0({i``mode}, {o``mode``0}); \
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mod m``mode``1($unsigned(i``mode), o``mode``1); \
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mod m``mode``2({i``mode[1:0]}, o``mode``2); \
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mod m``mode``3({$signed(i``mode)}, o``mode``3); \
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mod m``mode``4($unsigned({i``mode}), o``mode``4);
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`INSTANCES(u)
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`INSTANCES(s)
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`undef INSTANCES
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endmodule
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module gold(
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input [1:0] iu, is,
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output [2:0] `OUTPUTS(u), `OUTPUTS(s)
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);
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`define INSTANCES(mode) \
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assign o``mode``0 = i``mode; \
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assign o``mode``1 = i``mode; \
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assign o``mode``2 = i``mode; \
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assign o``mode``3 = i``mode; \
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assign o``mode``4 = i``mode;
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`INSTANCES(u)
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`INSTANCES(s)
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`undef INSTANCES
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endmodule
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module mod(
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input [2:0] inp,
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output [2:0] out
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);
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assign out = inp;
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endmodule
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