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				| APPNOTE_011_Design_Investigation | Finished AppNote 011 | 2013-12-08 15:12:32 +01:00 | 
		
			
			
			
			
				| CHAPTER_Eval | Renamed manual/FILES_* directories | 2014-01-28 06:55:47 +01:00 | 
		
			
			
			
			
				| CHAPTER_Prog | Renamed manual/FILES_* directories | 2014-01-28 06:55:47 +01:00 | 
		
			
			
			
			
				| CHAPTER_StateOfTheArt | Renamed manual/FILES_* directories | 2014-01-28 06:55:47 +01:00 | 
		
			
			
			
			
				| PRESENTATION_ExSyn | presentation progress | 2014-02-02 17:57:14 +01:00 | 
		
			
			
			
			
				| PRESENTATION_Intro | presentation progress | 2014-01-29 15:56:58 +01:00 | 
		
			
			
			
			
				| .gitignore | presentation progress | 2014-01-29 12:15:38 +01:00 | 
		
			
			
			
			
				| APPNOTE_010_Verilog_to_BLIF.tex | Fixed bug in example prog in appnote 011 | 2013-12-05 18:15:14 +01:00 | 
		
			
			
			
			
				| APPNOTE_011_Design_Investigation.tex | Finished AppNote 011 | 2013-12-08 15:12:32 +01:00 | 
		
			
			
			
			
				| appnotes.sh | Added first presentation slides | 2014-01-27 17:08:19 +01:00 | 
		
			
			
			
			
				| CHAPTER_Appnotes.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Approach.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Auxlibs.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Auxprogs.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Basics.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_CellLib.tex | Added $assert cell | 2014-01-19 14:03:40 +01:00 | 
		
			
			
			
			
				| CHAPTER_Eval.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Intro.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Optimize.tex | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| CHAPTER_Overview.tex | Updated manual | 2013-09-15 11:41:05 +02:00 | 
		
			
			
			
			
				| CHAPTER_Prog.tex | Renamed manual/FILES_* directories | 2014-01-28 06:55:47 +01:00 | 
		
			
			
			
			
				| CHAPTER_StateOfTheArt.tex | Renamed manual/FILES_* directories | 2014-01-28 06:55:47 +01:00 | 
		
			
			
			
			
				| CHAPTER_Techmap.tex | Moved common techlib files to techlibs/common | 2013-09-15 11:52:57 +02:00 | 
		
			
			
			
			
				| CHAPTER_Verilog.tex | Added RTLIL and Liberty syntax highlighting to manual | 2013-07-25 14:00:16 +02:00 | 
		
			
			
			
			
				| command-reference-manual.tex | Updated manual/command-reference-manual.tex | 2013-12-28 12:14:47 +01:00 | 
		
			
			
			
			
				| literature.bib | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 | 
		
			
			
			
			
				| manual.sh | Added first presentation slides | 2014-01-27 17:08:19 +01:00 | 
		
			
			
			
			
				| manual.tex | Fixed comments in manual rtlil/ilang syntax | 2013-07-25 15:01:02 +02:00 | 
		
			
			
			
			
				| presentation.sh | presentation progress | 2014-02-02 17:57:14 +01:00 | 
		
			
			
			
			
				| presentation.tex | presentation progress | 2014-02-02 13:30:49 +01:00 | 
		
			
			
			
			
				| PRESENTATION_ExSyn.tex | presentation progress | 2014-02-02 17:57:14 +01:00 | 
		
			
			
			
			
				| PRESENTATION_Intro.tex | Progress on presentation | 2014-01-31 12:48:31 +01:00 | 
		
			
			
			
			
				| weblinks.bib | Added Yosys Manual | 2013-07-20 15:19:12 +02:00 |