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https://github.com/YosysHQ/yosys
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60 lines
1.3 KiB
Text
60 lines
1.3 KiB
Text
read_rtlil <<EOT
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module \module137
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wire input 1 \clk
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wire width 1 output 1 \qa
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wire width 1 \qb
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cell $dff \dffa
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parameter \CLK_POLARITY 1
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parameter \WIDTH 1
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connect \CLK \clk
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connect \D \qb
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connect \Q \qa
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end
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cell $dff \dffb
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parameter \CLK_POLARITY 1
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parameter \WIDTH 1
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connect \CLK \clk
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connect \D 1'x
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connect \Q \qb
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end
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end
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EOT
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equiv_opt -assert opt_dff -sat
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design -reset
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read_rtlil <<EOT
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module \module137
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wire output 1 width 9 $2\reg204[8:0]
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wire input 1 \clk
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wire width 9 $auto$wreduce.cc:514:run$19340
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wire width 9 $auto$wreduce.cc:514:run$19341
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wire width 15 \dffout
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attribute \init 9'000000000
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wire width 9 \reg204
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cell $dff $auto$ff.cc:266:slice$26225
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parameter \CLK_POLARITY 1
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parameter \WIDTH 15
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connect \CLK \clk
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connect \D { 9'x \reg204 [8:3] }
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connect \Q \dffout
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end
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cell $dff $auto$ff.cc:266:slice$26292
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parameter \CLK_POLARITY 1
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parameter \WIDTH 9
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connect \CLK \clk
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connect \D $2\reg204[8:0]
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connect \Q \reg204
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end
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cell $mux $procmux$4510
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parameter \WIDTH 9
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connect \A 9'x
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connect \B 9'x
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connect \S 1'x
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connect \Y $auto$wreduce.cc:514:run$19340
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end
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connect $2\reg204[8:0] $auto$wreduce.cc:514:run$19340
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connect $auto$wreduce.cc:514:run$19341 [8:3] 6'000000
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end
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EOT
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equiv_opt -assert opt_dff -sat
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