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f8325f66b7
If the `$ge` cell we are replacing has wide output port, the upper bits on the port should be driven to zero. That's not what a `$not` cell with a single-bit input does. Instead opt for a `$logic_not` cell, which does zero-pad its output. Fixes #3867.
7 lines
140 B
Text
7 lines
140 B
Text
read_verilog <<EOF
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module test (input signed [4:0] i, output [5:0] o);
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assign o = (i >= 0);
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endmodule
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EOF
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equiv_opt -assert opt_expr -fine
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