mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
67b4ce06e0
This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
33 lines
518 B
Text
33 lines
518 B
Text
bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
|
|
init 1
|
|
abits 13 @M1
|
|
dbits 1 @M1
|
|
abits 12 @M2
|
|
dbits 2 @M2
|
|
abits 11 @M3
|
|
dbits 4 @M3
|
|
abits 10 @M4
|
|
dbits 8 @M4
|
|
abits 10 @M5
|
|
dbits 9 @M5
|
|
abits 9 @M6
|
|
dbits 16 @M6
|
|
abits 9 @M7
|
|
dbits 18 @M7
|
|
abits 8 @M8
|
|
dbits 32 @M8
|
|
abits 8 @M9
|
|
dbits 36 @M9
|
|
groups 2
|
|
ports 1 1
|
|
wrmode 0 1
|
|
enable 1 1
|
|
transp 0 0
|
|
clocks 2 3
|
|
clkpol 2 3
|
|
endbram
|
|
|
|
match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
|
|
min efficiency 2
|
|
make_transp
|
|
endmatch
|