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be04d8834e
yosys
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passes
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Marcelina Kościelnicka
4451f7f5e9
memory_bram: Some refactoring
...
This will make more sense when the new transparency masks land.
Fixes
#2902
.
2021-08-01 16:51:24 +02:00
..
cmds
rtlil: Make Process handling more uniform with Cell and Wire.
2021-07-12 00:47:34 +02:00
equiv
fsm
hierarchy
Use new read_id_num helper function elsewhere in hierarchy.cc
2021-07-20 10:13:15 -04:00
memory
memory_bram: Some refactoring
2021-08-01 16:51:24 +02:00
opt
opt_lut: Allow more than one -dlogic per cell type.
2021-07-29 17:30:07 +02:00
pmgen
proc
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
sat
memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
techmap
tests