mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-26 02:25:35 +00:00
bc66dfd9ea
The following SV module at HEAD imported with verific,
```systemverilog
module my_module(
input logic [4:0] a,
input logic clk,
input logic enable,
output logic [4:0] z
);
reg [4:0] pipeline_register;
always @(posedge clk) begin
pipeline_register <= enable ? a : pipeline_register;
end
assign z = pipeline_register;
endmodule : my_module
```
results in the following output verilog
```systemverilog
/* Generated by 0.36 */
(* top = 1 *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
wire [4:0] _0_;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
input [4:0] a;
wire [4:0] a;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
input clk;
wire clk;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
input enable;
wire enable;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
output [4:0] z;
wire [4:0] z;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
\$aldff #(
.ALOAD_POLARITY(32'd1),
.CLK_POLARITY(32'd1),
.WIDTH(32'd5)
) _1_ (
.AD(5'hxx),
.ALOAD(1'h0),
.CLK(clk),
.D(_0_),
.Q(z)
);
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
\$mux #(
.WIDTH(32'd5)
) _2_ (
.A(z),
.B(a),
.S(enable),
.Y(_0_)
);
endmodule
```
Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.
My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
|
||
|---|---|---|
| .. | ||
| aiger | ||
| ast | ||
| blif | ||
| json | ||
| liberty | ||
| rpc | ||
| rtlil | ||
| verific | ||
| verilog | ||