Miodrag Milanović 4525e419f6 Merge pull request #3120 from Icenowy/anlogic-bram ... anlogic: support BRAM mapping		2022-01-19 08:49:58 +01:00
..
aiger
arch	anlogic: support BRAM mapping	2021-12-17 20:28:22 +08:00
asicworld
bind	Add support for parsing the SystemVerilog 'bind' construct	2021-07-16 09:31:39 -04:00
blif	tests/blif: Add missing gitignore	2021-05-20 12:49:51 +02:00
bram	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
errors
fsm
hana
liberty
lut
memfile
memories	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
opt	memory_share: Fix SAT-based sharing for wide ports.	2021-12-20 18:40:14 +01:00
opt_share
proc	proc_prune: Make assign removal and promotion per-bit, remember promoted bits.	2021-08-14 15:26:11 +02:00
realmath
rpc
sat
select
share
simple	fix iverilog compatibility for new case expr tests	2022-01-03 12:11:41 -07:00
simple_abc9
smv
sva
svinterfaces	Add a test for interfaces on modules loaded on-demand	2021-07-14 22:54:50 -04:00
svtypes	sv: improve support for wire and var with user-defined types	2021-08-12 22:41:41 -06:00
techmap	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
tools	Fixes in vcdcd.pl for newer Perl versions	2021-10-19 10:56:43 +02:00
unit
various	logger: fix unmatched expected warnings and errors	2022-01-04 13:39:34 -07:00
verilog	sv: auto add nosync to certain always_comb local vars	2022-01-07 22:53:22 -07:00
vloghtb	Use HTTPS for website links, gatecat email	2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh