yosys/tests/verilog/prefix.ys at bbf65702a1859d7216f71e1df1193dca6c49cabf - mirrors/yosys - Libre-Chip.org

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Zachary Snow 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues

- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes

2021-09-21 12:10:59 -04:00

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 read_verilog -sv prefix.sv
 hierarchy
 proc
 select -module top
 sat -verify -seq 1 -prove-asserts -show-all