mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-14 04:48:46 +00:00
4 lines
90 B
Verilog
4 lines
90 B
Verilog
module test(input [2:0] in, output out);
|
|
assign out = !(in[0] & in[1] & in[2]);
|
|
endmodule
|