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23 lines
284 B
Verilog
23 lines
284 B
Verilog
module top (
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out,
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clk,
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in
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);
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output [7:0] out;
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input signed clk, in;
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reg signed [7:0] out = 0;
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always @(posedge clk)
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begin
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`ifndef BUG
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out <= out >> 1;
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out[7] <= in;
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`else
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out <= out << 1;
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out[7] <= in;
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`endif
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end
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endmodule
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