mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 18:05:24 +00:00
12 lines
99 B
Verilog
12 lines
99 B
Verilog
module top
|
|
(
|
|
input [5:0] x,
|
|
input [5:0] y,
|
|
|
|
output [11:0] A,
|
|
);
|
|
|
|
assign A = x * y;
|
|
|
|
endmodule
|