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https://github.com/YosysHQ/yosys
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6f1c137989
Commits65924fd1,abc40924, andebe29b66hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
55 lines
1.4 KiB
Bash
Executable file
55 lines
1.4 KiB
Bash
Executable file
#!/bin/bash
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set -e
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OPTIND=1
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abcprog="../../yosys-abc" # default to built-in version of abc
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while getopts "A:" opt
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do
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case "$opt" in
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A) abcprog="$OPTARG" ;;
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esac
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done
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shift "$((OPTIND-1))"
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# NB: *.aag and *.aig must contain a symbol table naming the primary
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# inputs and outputs, otherwise ABC and Yosys will name them
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# arbitrarily (and inconsistently with each other).
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for aag in *.aag; do
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# Since ABC cannot read *.aag, read the *.aig instead
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# (which would have been created by the reference aig2aig utility,
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# available from http://fmv.jku.at/aiger/)
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echo "Checking $aag."
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$abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
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../../yosys -qp "
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read_verilog ${aag%.*}_ref.v
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prep
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design -stash gold
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read_aiger -clk_name clock $aag
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prep
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 16 miter
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"
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done
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for aig in *.aig; do
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echo "Checking $aig."
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$abcprog -q "read -c $aig; write ${aig%.*}_ref.v"
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../../yosys -qp "
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read_verilog ${aig%.*}_ref.v
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prep
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design -stash gold
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read_aiger -clk_name clock $aig
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prep
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 16 miter
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"
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done
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