mirror of
https://github.com/YosysHQ/yosys
synced 2026-08-14 18:05:55 +00:00
10 lines
252 B
Verilog
10 lines
252 B
Verilog
module dffsr_mixedpol(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
|
|
|
|
always @(posedge CLK, negedge CLEAR, posedge PRESET)
|
|
if (PRESET) Q <= 1'b1;
|
|
else if (~CLEAR) Q <= 1'b0;
|
|
else Q <= ~D;
|
|
|
|
assign QN = ~Q;
|
|
|
|
endmodule
|