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2b270b2270
Makefiles now have `clean` target. Also fixed top level makefile calls to images directory. More yosys scripts instead of inline yosys commands in makefiles (which also means they can be included in the accompanying document when talking about the image generated). Fixed another couple image generators that were still outputting pdf directly. Fixed some hanging image references which hadn't been updated. Adjusted some text related to images, and included a couple more intermediate images on `memdemo`.
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147 lines
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Example(s)
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----------
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.. _sec:typusecase:
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Typical use case
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~~~~~~~~~~~~~~~~
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The following example script may be used in a synthesis flow to convert the
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behavioural Verilog code from the input file design.v to a gate-level netlist
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synth.v using the cell library described by the Liberty file :
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.. code:: yoscrypt
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:number-lines:
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#. read input file to internal representation
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read_verilog design.v
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#. convert high-level behavioral parts ("processes") to d-type flip-flops and muxes
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proc
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#. perform some simple optimizations
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opt
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#. convert high-level memory constructs to d-type flip-flops and multiplexers
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memory
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#. perform some simple optimizations
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opt
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#. convert design to (logical) gate-level netlists
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techmap
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#. perform some simple optimizations
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opt
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#. map internal register types to the ones from the cell library
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dfflibmap -liberty cells.lib
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#. use ABC to map remaining logic to cells from the cell library
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abc -liberty cells.lib
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#. cleanup
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opt
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#. write results to output file
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write_verilog synth.v
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A detailed description of the commands available in Yosys can be found in
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:ref:`cmd_ref`.
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Simple synthesis script
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~~~~~~~~~~~~~~~~~~~~~~~
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This section covers an example project available in
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``docs/source/code_examples/intro/*``. The project contains a simple ASIC
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synthesis script (``counter.ys``), a digital design written in Verilog
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(``counter.v``), and a simple CMOS cell library (``mycells.lib``).
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/intro/counter.ys``
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.. role:: yoscrypt(code)
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:language: yoscrypt
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#. :yoscrypt:`read_verilog counter.v` - Read Verilog source file and convert to
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internal representation.
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#. :yoscrypt:`hierarchy -check -top counter` - Elaborate the design hierarchy.
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Should always be the first command after reading the design. Can re-run AST front-end.
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#. :yoscrypt:`proc` - Convert ``processes`` (the internal representation of
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behavioral Verilog code) into multiplexers and registers.
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#. :yoscrypt:`opt` - Perform some basic optimizations and cleanups.
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#. :yoscrypt:`fsm` - Analyze and optimize finite state machines.
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#. :yoscrypt:`opt` - Perform some basic optimizations and cleanups.
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#. :yoscrypt:`memory` - Analyze memories and create circuits to implement them.
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#. :yoscrypt:`opt` - Perform some basic optimizations and cleanups.
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#. :yoscrypt:`techmap` - Map coarse-grain RTL cells (adders, etc.) to fine-grain
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logic gates (AND, OR, NOT, etc.).
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#. :yoscrypt:`opt` - Perform some basic optimizations and cleanups.
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#. :yoscrypt:`dfflibmap -liberty mycells.lib` - Map registers to available
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hardware flip-flops.
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#. :yoscrypt:`abc -liberty mycells.lib` - Map logic to available hardware gates.
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#. :yoscrypt:`clean` - Clean up the design (just the last step of
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:cmd:ref:`opt`).
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#. :yoscrypt:`write_verilog synth.v` - Write final synthesis result to output
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file.
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Running the script
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^^^^^^^^^^^^^^^^^^
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.. literalinclude:: /code_examples/intro/counter.v
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:language: Verilog
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:caption: ``docs/source/code_examples/intro/counter.v``
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.. literalinclude:: /code_examples/intro/mycells.lib
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:language: Liberty
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:caption: ``docs/source/code_examples/intro/mycells.lib``
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Step 1
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""""""
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 1-3
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Result:
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.. figure:: /_images/code_examples/intro/counter_00.*
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:class: width-helper
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Step 2
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""""""
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 5-6
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Result:
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.. figure:: /_images/code_examples/intro/counter_01.*
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:class: width-helper
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Step 3
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""""""
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 8-9
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Result:
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.. figure:: /_images/code_examples/intro/counter_02.*
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:class: width-helper
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Step 4
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""""""
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.. literalinclude:: /code_examples/intro/counter.ys
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:language: yoscrypt
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:lines: 11-18
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Result:
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.. figure:: /_images/code_examples/intro/counter_03.*
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:class: width-helper
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