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Code Activity
yosys/techlibs/ice40
History
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
2018-04-18 16:55:12 -07:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v Improving vpr output support. 2018-04-18 16:55:12 -07:00
cells_sim.v Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
ice40_ffinit.cc Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
ice40_ffssr.cc Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
ice40_opt.cc
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Makefile.inc Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
synth_ice40.cc Improving vpr output support. 2018-04-18 16:55:12 -07:00