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9 lines
356 B
Plaintext
9 lines
356 B
Plaintext
read_verilog bram_tdp.v
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hierarchy -top BRAM_TDP
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synth_quicklogic -family qlf_k6n10f
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read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
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read_verilog -formal bram_tdp_tb.v
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hierarchy -top TB
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proc
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sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd
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