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tests
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Update filenames and location for test script
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2025-09-25 15:44:05 +01:00 |
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arith_map_ccu2c.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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arith_map_ccu2d.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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arith_map_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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brams_8kc.txt
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lattice: Disable broken port configuration in bram inference
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2023-12-21 10:47:40 +01:00 |
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brams_16kd.txt
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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brams_map_8kc.v
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lattice: Fix mapping onto DP8KC for data width 1 or 2
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2023-12-20 23:42:12 +01:00 |
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brams_map_16kd.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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brams_map_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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brams_nexus.txt
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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ccu2c_sim.vh
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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ccu2d_sim.vh
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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cells_bb_ecp5.v
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Special DP16KD model is required
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2025-09-25 15:38:55 +01:00 |
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cells_bb_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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cells_bb_xo2.v
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enable more primitives supported with nextpnr
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2023-08-25 11:45:25 +02:00 |
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cells_bb_xo3.v
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enable more primitives supported with nextpnr
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2023-08-25 11:45:25 +02:00 |
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cells_bb_xo3d.v
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enable more primitives supported with nextpnr
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2023-08-25 11:45:25 +02:00 |
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cells_ff.vh
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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cells_io.vh
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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cells_map_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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cells_map_trellis.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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cells_sim_ecp5.v
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Special DP16KD model is required
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2025-09-25 15:38:55 +01:00 |
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cells_sim_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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cells_sim_xo2.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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cells_sim_xo3.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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cells_sim_xo3d.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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cells_xtra.py
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Special DP16KD model is required
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2025-09-25 15:38:55 +01:00 |
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cells_xtra_nexus.py
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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common_sim.vh
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Delete synth_ecp5
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2025-09-25 15:44:03 +01:00 |
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dsp_map_18x18.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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dsp_map_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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latches_map.v
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Create synth_lattice
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2023-08-23 10:53:21 +02:00 |
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lattice_gsr.cc
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ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
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2023-08-22 10:50:11 +02:00 |
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lrams_map_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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lrams_nexus.txt
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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lutrams_map_nexus.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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lutrams_map_trellis.v
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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lutrams_nexus.txt
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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lutrams_trellis.txt
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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Makefile.inc
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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parse_init.vh
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
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synth_lattice.cc
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synth_nexus to synth_lattice
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2025-09-26 19:45:03 +01:00 |
