mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
7203ba7bc1
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
45 lines
1.9 KiB
C
45 lines
1.9 KiB
C
/*
|
|
* yosys -- Yosys Open SYnthesis Suite
|
|
*
|
|
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
|
*
|
|
* Permission to use, copy, modify, and/or distribute this software for any
|
|
* purpose with or without fee is hereby granted, provided that the above
|
|
* copyright notice and this permission notice appear in all copies.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
*
|
|
*/
|
|
|
|
#ifndef SIMPLEMAP_H
|
|
#define SIMPLEMAP_H
|
|
|
|
#include "kernel/yosys.h"
|
|
|
|
YOSYS_NAMESPACE_BEGIN
|
|
|
|
extern void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
extern void simplemap(RTLIL::Module *module, RTLIL::Cell *cell);
|
|
|
|
extern void simplemap_get_mappers(dict<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
|
|
|
|
YOSYS_NAMESPACE_END
|
|
|
|
#endif
|