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9925b27432
Drop the parts that are being dropped. Move the things that are being moved. Also move the verilog stuff out of README and into the docs. GettingStarted is less cut and dry, so hold off on that one.
42 lines
1.4 KiB
ReStructuredText
42 lines
1.4 KiB
ReStructuredText
.. _chapter:overview:
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Yosys internals
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===============
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.. todo:: less academic
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Yosys is an extensible open source hardware synthesis tool. It is aimed at
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designers who are looking for an easily accessible, universal, and
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vendor-independent synthesis tool, as well as scientists who do research in
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electronic design automation (EDA) and are looking for an open synthesis
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framework that can be used to test algorithms on complex real-world designs.
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Yosys can synthesize a large subset of Verilog 2005 and has been tested with a
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wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
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`openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_.
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.. todo:: add RISC-V core example
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.. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200
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.. _openMSP430 CPU: http://opencores.org/projects/openmsp430
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.. _OpenCores I2C master: http://opencores.org/projects/i2c
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.. _k68 CPU: http://opencores.org/projects/k68
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Yosys is written in C++, targeting C++17 at minimum. This chapter describes some
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of the fundamental Yosys data structures. For the sake of simplicity the C++
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type names used in the Yosys implementation are used in this chapter, even
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though the chapter only explains the conceptual idea behind it and can be used
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as reference to implement a similar system in any language.
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.. toctree::
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:maxdepth: 3
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flow/index
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formats/index
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extending_yosys/index
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techmap
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verilog
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