mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
b9b5899cce
* Copies guidelines files into docs/ for website * Copying manual/CHAPTER_Prog for new docs * Copying manual/APPNOTE_011... for new docs Also adding faketime to list of packages for website build. Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>
20 lines
332 B
Verilog
20 lines
332 B
Verilog
module memdemo(clk, d, y);
|
|
|
|
input clk;
|
|
input [3:0] d;
|
|
output reg [3:0] y;
|
|
|
|
integer i;
|
|
reg [1:0] s1, s2;
|
|
reg [3:0] mem [0:3];
|
|
|
|
always @(posedge clk) begin
|
|
for (i = 0; i < 4; i = i+1)
|
|
mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4];
|
|
{ s2, s1 } = d ? { s1, s2 } ^ d : 4'b0;
|
|
mem[s1] <= d;
|
|
y <= mem[s2];
|
|
end
|
|
|
|
endmodule
|