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Code Activity
yosys/frontends
History
Xing Guo c30fd46ea3 Fix handling of cases that look like sva labels again. 
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels.  After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:

```
➜  /tmp yosys -p 'read -sv a1.v'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)

-- Running command `read -sv a1.v' --

1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜  /tmp cat a1.v
module test(input wire A);
  localparam TEST = 1;
  always_comb begin
    case (A)
      TEST: assert(1);
    endcase
  end
endmodule
```

We encountered this issue before but with a different error message[^1],

[^1]: https://github.com/YosysHQ/yosys/issues/862
2025-09-05 11:54:13 +08:00
..
aiger rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
aiger2 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
ast simplify: fix $initstate segfault 2025-08-12 12:39:36 +02:00
blif rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
json fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
liberty Liberty file caching with new libcache command 2025-04-03 13:39:35 +02:00
rpc Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
rtlil read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
verific verificsva: Fix typo in the cover only followed-by operator support 2025-08-04 15:38:19 +02:00
verilog Fix handling of cases that look like sva labels again. 2025-09-05 11:54:13 +08:00