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Test cases from https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071; In both cases synthesized only LUTs and DFFs.
16 lines
237 B
Verilog
16 lines
237 B
Verilog
module top(data, addr);
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output [3:0] data;
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input [4:0] addr;
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always @(addr) begin
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case (addr)
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0 : data = 'h4;
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1 : data = 'h9;
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2 : data = 'h1;
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15 : data = 'h8;
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16 : data = 'h1;
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17 : data = 'h0;
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default : data = 'h0;
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endcase
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end
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endmodule
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