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71 lines
1.7 KiB
Text
71 lines
1.7 KiB
Text
read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:NX_CY
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select -assert-count 4 t:NX_LUT
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select -assert-none t:NX_CY t:NX_LUT %% t:* %D
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design -reset
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read_verilog <<EOT
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module top
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(
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input [5:0] x,
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input [5:0] y,
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output [5:0] A,
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input CI,
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output CO
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);
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assign {CO, A} = x + y + CI;
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endmodule
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EOT
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hierarchy -top top
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proc
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equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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stat
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select -assert-count 2 t:NX_CY
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select -assert-none t:NX_CY %% t:* %D
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design -reset
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read_verilog <<EOT
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module top
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(
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input [189:0] x,
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input [189:0] y,
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output [189:0] A
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);
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assign A = x + y;
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endmodule
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EOT
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hierarchy -top top
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proc
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equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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stat
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select -assert-count 48 t:NX_CY
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select -assert-none t:NX_CY %% t:* %D
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