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56 lines
1.8 KiB
Text
56 lines
1.8 KiB
Text
read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:DFFC
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:LUT1
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFF
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select -assert-count 1 t:LUT2
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFF t:LUT2 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFNR
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select -assert-count 1 t:LUT1
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D
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