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https://github.com/YosysHQ/yosys
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db5b76edc1
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this. |
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|---|---|---|
| .. | ||
| aiger | ||
| alumacc | ||
| arch | ||
| asicworld | ||
| bind | ||
| blif | ||
| bram | ||
| cxxrtl | ||
| errors | ||
| fmt | ||
| fsm | ||
| functional | ||
| hana | ||
| liberty | ||
| lut | ||
| memfile | ||
| memlib | ||
| memories | ||
| opt | ||
| opt_share | ||
| proc | ||
| realmath | ||
| rpc | ||
| sat | ||
| select | ||
| share | ||
| sim | ||
| simple | ||
| simple_abc9 | ||
| smv | ||
| sva | ||
| svinterfaces | ||
| svtypes | ||
| techmap | ||
| tools | ||
| unit | ||
| various | ||
| verific | ||
| verilog | ||
| vloghtb | ||
| xprop | ||
| gen-tests-makefile.sh | ||