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71dd412ac5
- Add -map and -assert options for equiv_opt; !!! '-assert' option was commented for the next tests (unproven $equiv cells was found): - dffs; - div_mod; - latches; - mul_pow; - Add design -load; - Remove simulations;
24 lines
263 B
Verilog
24 lines
263 B
Verilog
module tristate (en, i, o);
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input en;
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input i;
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output reg o;
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always @(en or i)
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o <= (en)? i : 1'bZ;
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endmodule
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module top (
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input en,
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input a,
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output b
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);
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tristate u_tri (
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.en (en ),
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.i (a ),
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.o (b )
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);
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endmodule
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