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Code
Activity
b818e1c8ca
yosys
/
techlibs
/
xilinx
History
Miodrag Milanovic
a689342207
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
..
tests
abc9_model.v
arith_map.v
brams_defs.vh
brams_xc2v.txt
brams_xc2v_map.v
brams_xc3sda.txt
brams_xc3sda_map.v
brams_xc4v.txt
brams_xc4v_map.v
brams_xc5v_map.v
brams_xc6v_map.v
brams_xcu_map.v
brams_xcv.txt
brams_xcv_map.v
cells_map.v
cells_sim.v
cells_xtra.py
cells_xtra.v
CMakeLists.txt
ff_map.v
lut_map.v
lutrams_xc5v.txt
lutrams_xc5v_map.v
lutrams_xcu.txt
lutrams_xcv.txt
lutrams_xcv_map.v
mux_map.v
synth_xilinx.cc
urams.txt
urams_map.v
xc3s_mult_map.v
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_dsp_map.v
xc7_dsp_map.v
xcu_dsp_map.v
xilinx_dffopt.cc
xilinx_dsp.cc
xilinx_dsp.pmg
xilinx_dsp48a.pmg
xilinx_dsp_cascade.pmg
xilinx_dsp_CREG.pmg
xilinx_srl.cc
xilinx_srl.pmg