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yosys/kernel
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00
..
bitpattern.h
calc.cc
cellaigs.cc Fixes for OAI4 cell implementation 2019-04-23 17:54:00 +01:00
cellaigs.h
celledges.cc
celledges.h
celltypes.h Add $specrule cells for $setup/$hold/$skew specify rules 2019-04-23 21:36:59 +02:00
consteval.h Improve ConstEval error handling for non-eval cell types 2018-11-29 05:07:40 +01:00
cost.h
driver.cc fix codestyle formatting 2019-04-29 19:20:33 +09:00
hashlib.h Add hashlib "<container>::element(int n)" methods 2019-03-14 22:04:42 +01:00
log.cc Add log_debug() framework 2019-04-22 17:25:52 +02:00
log.h Add log_debug() framework 2019-04-22 17:25:52 +02:00
macc.h
modtools.h
register.cc Add log_debug() framework 2019-04-22 17:25:52 +02:00
register.h
rtlil.cc Add rewrite_sigspecs2, Improve remove() wires 2019-05-15 16:01:00 +02:00
rtlil.h Add rewrite_sigspecs2, Improve remove() wires 2019-05-15 16:01:00 +02:00
satgen.h
sigtools.h
utils.h
yosys.cc Optimize ceil_log2 function 2019-05-07 12:17:56 -05:00
yosys.h Optimize ceil_log2 function 2019-05-07 12:17:56 -05:00