mirror of
https://github.com/YosysHQ/yosys
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135 lines
4.1 KiB
C++
135 lines
4.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2019 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct LatticeGsrPass : public Pass {
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LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" lattice_gsr [options] [selection]\n");
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log("\n");
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log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
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log("if a GSR or SGSR primitive is used in the design.\n");
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log("\n");
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log("If any cell has the GSR parameter set to \"AUTO\", this will be resolved\n");
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log("to \"ENABLED\" if a GSR primitive is present and the (* nogsr *) attribute\n");
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log("is not set, otherwise it will be resolved to \"DISABLED\".\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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log("Handling GSR in %s.\n", log_id(module));
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SigMap sigmap(module);
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SigBit gsr;
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bool found_gsr = false;
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for (auto cell : module->selected_cells())
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{
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if (cell->type != ID(GSR) && cell->type != ID(SGSR))
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continue;
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if (found_gsr)
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log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module));
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found_gsr = true;
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SigSpec sig_gsr = cell->getPort(ID(GSR));
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if (GetSize(sig_gsr) < 1)
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log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell));
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gsr = sigmap(sig_gsr[0]);
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}
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// Resolve GSR parameter
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for (auto cell : module->selected_cells())
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{
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if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
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continue;
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bool gsren = found_gsr;
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if (cell->get_bool_attribute(ID(nogsr)))
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gsren = false;
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cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
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}
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if (!found_gsr)
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continue;
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// For finding active low FF inputs
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pool<SigBit> inverted_gsr;
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log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr));
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for (auto cell : module->selected_cells())
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{
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if (cell->type != ID($_NOT_))
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continue;
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SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y);
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if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
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continue;
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SigBit a = sigmap(sig_a[0]);
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if (a == gsr)
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inverted_gsr.insert(sigmap(sig_y[0]));
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}
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for (auto cell : module->selected_cells())
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{
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if (cell->type != ID(TRELLIS_FF))
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continue;
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if (cell->getParam(ID(GSR)).decode_string() != "ENABLED")
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continue;
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if (cell->getParam(ID(SRMODE)).decode_string() != "ASYNC")
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continue;
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SigSpec sig_lsr = cell->getPort(ID(LSR));
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if (GetSize(sig_lsr) < 1)
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continue;
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SigBit lsr = sigmap(sig_lsr[0]);
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if (!inverted_gsr.count(lsr))
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continue;
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cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
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cell->unsetPort(ID(LSR));
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}
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}
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}
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} LatticeGsrPass;
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PRIVATE_NAMESPACE_END
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