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54 lines
1.1 KiB
Text
54 lines
1.1 KiB
Text
read_verilog <<EOT
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module top(input A, B, CI, output O, CO);
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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.CI(CI),
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.CO(CO)
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);
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SB_LUT4 #(
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.LUT_INIT(16'b 0110_1001_1001_0110)
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) adder (
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.I0(1'b0),
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.I1(A),
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.I2(B),
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.I3(1'b0),
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.O(O)
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);
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endmodule
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EOT
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ice40_wrapcarry
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select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
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design -reset
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read_verilog <<EOT
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module top(input A, B, CI, output O, CO);
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(* foo = "bar", answer = 42, keep=0 *)
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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.CI(CI),
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.CO(CO)
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);
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(* keep, blah="blah", answer = 43 *)
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SB_LUT4 #(
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.LUT_INIT(16'b 0110_1001_1001_0110)
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) adder (
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.I0(1'b0),
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.I1(A),
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.I2(B),
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.I3(1'b0),
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.O(O)
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);
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endmodule
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EOT
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ice40_wrapcarry
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select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
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select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
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select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
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ice40_wrapcarry -unwrap
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select -assert-count 1 c:carry a:src=<<EOT:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
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select -assert-count 1 c:adder a:src=<<EOT:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
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