yosys/tests/verilog/asgn_expr.ys at b74d33d1b8329ecda69ff6889479a097d8835664 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-12 12:08:19 +00:00

Zachary Snow 4edb1a1921 sv: support assignments within expressions

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.

2023-09-05 22:27:55 -04:00

4 lines

72 B

Plaintext

Raw Blame History

	`read_verilog -sv asgn_expr.sv`
	`proc`
	`sat -verify -prove-asserts -show-all`