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https://github.com/YosysHQ/yosys
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b705c546ea
Replace module instances instead of module contents. This fixes parametrisable width mismatch with read_verilog frontend, but not verific frontend. |
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| .. | ||
| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| pmgen | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||