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45 lines
733 B
Text
45 lines
733 B
Text
# Baseline: no csa_tree
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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# Baseline synth
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techmap
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abc -g AND,OR,XOR
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opt_clean
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stat
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design -save baseline
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# With csa_tree
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design -reset
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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csa_tree
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techmap
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abc -g AND,OR,XOR
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opt_clean
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stat
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select -assert-max 250 t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NOT_ %u
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design -save csa_result
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# Depth comparison via ABC
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design -reset
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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techmap
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abc -D 1
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stat
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log "baseline depth mapping complete"
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design -reset
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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csa_tree
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techmap
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abc -D 1
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stat
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log "CSA depth mapping complete"
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