yosys/docs/source/code_examples/selections/select.ys at b6e61c16b148c4441a97f31726f4f14c042dd511 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-14 21:08:47 +00:00

Krystine Sherwin dbc38d72cf

docs: moving code examples

Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.

2023-11-14 12:55:39 +13:00

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 read_verilog select.v
 hierarchy -check -top test
 proc; opt
 cd test
 select -set cone_a state_a %ci*:-$dff
 select -set cone_b state_b %ci*:-$dff
 select -set cone_ab @cone_a @cone_b %i
 show -prefix select -format dot -notitle \
      -color red @cone_ab -color magenta @cone_a \
      -color blue @cone_b