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20 lines
690 B
Text
20 lines
690 B
Text
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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stat
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 6 t:CC_DFF
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select -assert-max 5 t:CC_LUT2
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select -assert-max 6 t:CC_LUT3
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select -assert-max 9 t:CC_LUT4
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select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
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