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1248af1e02
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
12 lines
272 B
Text
12 lines
272 B
Text
logger -expect error 'Cannot declare module port `\\x. within a generate block\.' 1
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read_verilog <<EOT
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module top(x);
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generate
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if (1) begin : blk
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output wire x;
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assign x = 1;
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end
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endgenerate
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output wire x;
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endmodule
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EOT
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