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yosys/tests/verilog/bug2493.ys
Krystine Sherwin 1248af1e02
Tests: Prefer single quotes for regex
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
2025-10-06 14:22:33 +13:00

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logger -expect error 'Failed to detect width for identifier \\genblk1\.y!' 1
read_verilog <<EOT
module top1;
wire x;
generate
if (1) begin
mod y();
assign x = y;
end
endgenerate
endmodule
EOT