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yosys/tests/verilog/block_labels.ys
Krystine Sherwin 1248af1e02
Tests: Prefer single quotes for regex
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
2025-10-06 14:22:33 +13:00

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read_verilog <<EOT
module foo;
genvar a;
for (a = 0; a < 10; a++) begin : a
end : a
endmodule
EOT
read_verilog <<EOT
module foo2;
genvar a;
for (a = 0; a < 10; a++) begin : a
end
endmodule
EOT
logger -expect error 'Begin label \(a\) and end label \(b\) don.t match\.' 1
read_verilog <<EOT
module foo3;
genvar a;
for (a = 0; a < 10; a++) begin : a
end : b
endmodule
EOT