mirror of
https://github.com/YosysHQ/yosys
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1248af1e02
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
142 lines
5.2 KiB
Text
142 lines
5.2 KiB
Text
logger -nowarn "Yosys has only limited support for tri-state logic at the moment. .*"
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logger -nowarn "Ignoring boxed module .*."
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read_verilog <<EOT
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module top(input C, D, output [7:0] Q);
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FDRE /*#(.INIT(0))*/ fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
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FDSE #(.INIT(0)) fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
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FDCE #(.INIT(0)) fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
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FDPE #(.INIT(0)) fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
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FDRE_1 #(.INIT(0)) fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
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FDSE_1 #(.INIT(0)) fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
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FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
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FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 6 t:FD*
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select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8
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design -reset
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read_verilog <<EOT
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module top(input C, D, output [7:0] Q);
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FDRE #(.INIT(0)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
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FDSE #(.INIT(0)) fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
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FDCE #(.INIT(0)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
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FDPE #(.INIT(0)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
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FDRE_1 /*#(.INIT(0))*/ fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
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FDSE_1 #(.INIT(0)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
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FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
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FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 4 t:FD*
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select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
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design -reset
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read_verilog <<EOT
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module top(input C, D, output [7:0] Q);
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FDRE #(.INIT(1)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
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FDSE /*#(.INIT(1))*/ fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
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FDCE #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
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FDPE #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
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FDRE_1 #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
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FDSE_1 #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
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FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
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FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
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endmodule
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EOT
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logger -expect warning 'Whitebox .\$paramod\\FDRE\\INIT=.*1. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
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logger -expect warning 'Whitebox .\$paramod\\FDRE_1\\INIT=.*1. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
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logger -expect warning 'Whitebox .FDSE. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
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logger -expect warning 'Whitebox .\$paramod\\FDSE_1\\INIT=.*1. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 8 t:FD*
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design -reset
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read_verilog <<EOT
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module top(input clk, clr, pre, output reg q0 = 1'b0, output reg q1 = 1'b1);
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always @(posedge clk or posedge clr)
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if (clr)
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q0 <= 1'b0;
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else
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q0 <= ~q0;
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always @(posedge clk or posedge pre)
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if (pre)
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q1 <= 1'b1;
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else
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q1 <= ~q1;
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endmodule
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EOT
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proc
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 1 t:FDCE
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select -assert-count 1 t:FDPE
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select -assert-count 2 t:INV
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select -assert-count 0 t:FD* t:INV %% t:* %D
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design -reset
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read_verilog <<EOT
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module top(input clk, input d, output q);
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reg r;
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always @(posedge clk) begin
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r <= d;
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end
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assign q = ~r;
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endmodule
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EOT
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proc
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 1 t:FDRE %co w:r %i
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design -reset
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read_verilog <<EOT
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module top(input clk, input a, b, output reg q1, output q2);
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reg r;
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always @(posedge clk) begin
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q1 <= a | b;
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r <= ~(~a & ~b);
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end
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assign q2 = r;
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endmodule
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EOT
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proc
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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design -load postopt
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select -assert-count 1 t:FDRE %co %a w:r %i
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design -reset
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read_verilog <<EOT
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module top(input clk, input a, b, output o);
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reg r1, r2;
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always @(posedge clk) begin
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r1 <= a | b;
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r2 <= ~(~a & ~b);
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end
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assign o = r1 | r2;
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endmodule
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EOT
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proc
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read_verilog -lib +/xilinx/cells_sim.v
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equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
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logger -expect-no-warnings
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