mirror of
https://github.com/YosysHQ/yosys
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915ad949f9
Without this check it's trivially easy to crash Yosys with a tiny RTLIL input by specifying a constant with very large width. Fuzz testers love hitting this over and over again.
838 lines
21 KiB
C++
838 lines
21 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* A handwritten recursive-descent parser for the RTLIL text representation.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "kernel/utils.h"
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#include <charconv>
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#include <deque>
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#include <optional>
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YOSYS_NAMESPACE_BEGIN
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struct RTLILFrontendWorker {
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// Forbid constants of more than 1 Gb.
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// This will help us not explode on malicious RTLIL.
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static constexpr int MAX_CONST_WIDTH = 1024 * 1024 * 1024;
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std::istream *f = nullptr;
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RTLIL::Design *design;
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bool flag_nooverwrite = false;
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bool flag_overwrite = false;
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bool flag_lib = false;
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int line_num;
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std::string line_buf;
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// Substring of line_buf. Always newline-terminated, thus never empty.
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std::string_view line;
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RTLIL::Module *current_module;
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dict<RTLIL::IdString, RTLIL::Const> attrbuf;
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std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
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std::vector<RTLIL::CaseRule*> case_stack;
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template <typename... Args>
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[[noreturn]]
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void error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
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{
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log_error("Parser error in line %d: %s\n", line_num, fmt.format(args...));
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}
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template <typename... Args>
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void warning(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
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{
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log_warning("In line %d: %s\n", line_num, fmt.format(args...));
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}
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// May return an empty line if the stream is not good().
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void advance_to_next_nonempty_line()
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{
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if (!f->good()) {
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line = "\n";
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return;
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}
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while (true) {
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std::getline(*f, line_buf);
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line_num++;
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if (line_buf.empty() || line_buf[line_buf.size() - 1] != '\n')
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line_buf += '\n';
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line = line_buf;
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consume_whitespace_and_comments();
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if (line[0] != '\n' || !f->good())
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break;
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}
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}
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void consume_whitespace_and_comments()
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{
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while (true) {
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switch (line[0]) {
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case ' ':
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case '\t':
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line = line.substr(1);
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break;
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case '#':
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line = "\n";
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return;
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default:
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return;
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}
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}
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}
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bool try_parse_keyword(std::string_view keyword)
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{
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int keyword_size = keyword.size();
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if (keyword != line.substr(0, keyword_size))
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return false;
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// This index is safe because `line` is always newline-terminated
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// and `keyword` never contains a newline.
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char ch = line[keyword_size];
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if (ch >= 'a' && ch <= 'z')
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return false;
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line = line.substr(keyword_size);
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consume_whitespace_and_comments();
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return true;
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}
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std::string error_token()
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{
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std::string result;
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for (char ch : line) {
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if (ch == '\n' || ch == ' ' || ch == '\t')
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break;
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result += ch;
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}
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return result;
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}
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void expect_keyword(std::string_view keyword)
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{
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if (!try_parse_keyword(keyword))
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error("Expected token `%s', got `%s'.", keyword, error_token());
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}
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bool try_parse_char(char ch)
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{
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if (line[0] != ch)
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return false;
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line = line.substr(1);
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consume_whitespace_and_comments();
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return true;
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}
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void expect_char(char ch)
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{
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if (!try_parse_char(ch))
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error("Expected `%c', got `%s'.", ch, error_token());
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}
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bool try_parse_eol()
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{
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if (line[0] != '\n')
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return false;
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advance_to_next_nonempty_line();
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return true;
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}
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void expect_eol()
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{
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if (!try_parse_eol())
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error("Expected EOL, got `%s'.", error_token());
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}
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std::optional<RTLIL::IdString> try_parse_id()
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{
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char ch = line[0];
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if (ch != '\\' && ch != '$')
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return std::nullopt;
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int idx = 1;
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while (true) {
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ch = line[idx];
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if (ch <= ' ' && (ch == ' ' || ch == '\t' || ch == '\n' || ch == '\r'))
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break;
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++idx;
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}
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IdString result(line.substr(0, idx));
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line = line.substr(idx);
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consume_whitespace_and_comments();
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return result;
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}
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RTLIL::IdString parse_id()
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{
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (!id.has_value())
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error("Expected ID, got `%s'.", error_token());
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return std::move(*id);
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}
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long long parse_integer()
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{
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long long result = parse_integer_alone();
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consume_whitespace_and_comments();
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return result;
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}
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long long parse_integer_alone()
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{
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int idx = 0;
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if (line[idx] == '-')
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++idx;
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while (true) {
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char ch = line[idx];
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if (ch < '0' || ch > '9')
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break;
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++idx;
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}
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long long result;
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if (std::from_chars(line.data(), line.data() + idx, result, 10).ec != std::errc{})
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error("Invalid integer `%s'.", error_token());
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line = line.substr(idx);
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return result;
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}
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std::string parse_string()
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{
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if (line[0] != '\"')
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error("Expected string, got `%s'.", error_token());
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std::string str;
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int idx = 1;
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while (true) {
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int start_idx = idx;
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char ch;
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while (true) {
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ch = line[idx];
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if (ch == '"' || ch == '\n' || ch == '\\' || ch == 0)
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break;
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++idx;
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}
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str.append(line.data() + start_idx, line.data() + idx);
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++idx;
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if (ch == '"')
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break;
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if (ch == 0)
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error("Null byte in string literal: `%s'.", line);
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if (ch == '\n')
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error("Unterminated string literal: `%s'.", line);
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ch = line[idx++];
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if (ch == 'n') {
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ch = '\n';
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} else if (ch == 't') {
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ch = '\t';
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} else if (ch >= '0' && ch <= '7') {
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int v = ch - '0';
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char next_ch = line[idx + 1];
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if (next_ch >= '0' && next_ch <= '7') {
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++idx;
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v = v*8 + (next_ch - '0');
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next_ch = line[idx + 1];
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if (next_ch >= '0' && next_ch <= '7') {
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++idx;
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v = v*8 + (next_ch - '0');
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}
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}
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ch = v;
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}
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str += ch;
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}
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line = line.substr(idx);
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consume_whitespace_and_comments();
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return str;
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}
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RTLIL::Const parse_const()
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{
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if (line[0] == '"')
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return RTLIL::Const(parse_string());
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bool negative_value = line[0] == '-';
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long long width = parse_integer_alone();
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// Can't test value<0 here because we need to stop parsing after '-0'
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if (negative_value || line[0] != '\'') {
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if (width < INT_MIN || width > INT_MAX)
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error("Integer %lld out of range before `%s'.", width, error_token());
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consume_whitespace_and_comments();
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return RTLIL::Const(width);
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}
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int idx = 1;
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bool is_signed = line[1] == 's';
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if (is_signed)
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++idx;
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std::vector<RTLIL::State> bits;
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if (width > MAX_CONST_WIDTH)
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error("Constant width %lld out of range before `%s`.", width, error_token());
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bits.reserve(width);
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while (true) {
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RTLIL::State bit;
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switch (line[idx]) {
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case '0': bit = RTLIL::S0; break;
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case '1': bit = RTLIL::S1; break;
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case 'x': bit = RTLIL::Sx; break;
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case 'z': bit = RTLIL::Sz; break;
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case 'm': bit = RTLIL::Sm; break;
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case '-': bit = RTLIL::Sa; break;
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default: goto done;
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}
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bits.push_back(bit);
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++idx;
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}
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done:
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std::reverse(bits.begin(), bits.end());
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if (GetSize(bits) > width)
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bits.resize(width);
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else if (GetSize(bits) < width) {
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RTLIL::State extbit = RTLIL::Sx;
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if (!bits.empty()) {
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extbit = bits.back();
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if (extbit == RTLIL::S1)
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extbit = RTLIL::S0;
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}
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bits.resize(width, extbit);
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}
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RTLIL::Const val(std::move(bits));
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if (is_signed)
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val.flags |= RTLIL::CONST_FLAG_SIGNED;
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line = line.substr(idx);
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consume_whitespace_and_comments();
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return val;
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}
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RTLIL::SigSpec parse_sigspec()
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{
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if (try_parse_char('{')) {
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std::vector<SigSpec> parts;
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while (!try_parse_char('}'))
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parts.push_back(parse_sigspec());
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RTLIL::SigSpec sig;
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for (auto it = parts.rbegin(); it != parts.rend(); ++it)
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sig.append(std::move(*it));
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return sig;
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}
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RTLIL::SigSpec sig;
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// We could add a special path for parsing IdStrings that must already exist,
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// as here.
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// We don't need to addref/release in this case.
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (id.has_value()) {
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RTLIL::Wire *wire = current_module->wire(*id);
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if (wire == nullptr)
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error("Wire `%s' not found.", *id);
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sig = RTLIL::SigSpec(wire);
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} else {
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sig = RTLIL::SigSpec(parse_const());
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}
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while (try_parse_char('[')) {
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int left = parse_integer();
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if (left >= sig.size() || left < 0)
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error("bit index %d out of range", left);
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if (try_parse_char(':')) {
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int right = parse_integer();
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if (right < 0)
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error("bit index %d out of range", right);
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if (left < right)
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error("invalid slice [%d:%d]", left, right);
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sig = sig.extract(right, left-right+1);
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} else {
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sig = sig.extract(left);
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}
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expect_char(']');
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}
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return sig;
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}
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void parse_module()
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{
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RTLIL::IdString module_name = parse_id();
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expect_eol();
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bool delete_current_module = false;
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if (design->has(module_name)) {
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RTLIL::Module *existing_mod = design->module(module_name);
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if (!flag_overwrite && (flag_lib || (attrbuf.count(ID::blackbox) && attrbuf.at(ID::blackbox).as_bool()))) {
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log("Ignoring blackbox re-definition of module %s.\n", module_name);
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delete_current_module = true;
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} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
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error("RTLIL error: redefinition of module %s.", module_name);
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} else if (flag_nooverwrite) {
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log("Ignoring re-definition of module %s.\n", module_name);
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delete_current_module = true;
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} else {
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log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", module_name);
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design->remove(existing_mod);
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}
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}
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current_module = new RTLIL::Module;
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current_module->name = std::move(module_name);
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current_module->attributes = std::move(attrbuf);
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if (!delete_current_module)
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design->add(current_module);
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while (true)
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{
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if (try_parse_keyword("attribute")) {
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parse_attribute();
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continue;
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}
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if (try_parse_keyword("parameter")) {
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parse_parameter();
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continue;
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}
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if (try_parse_keyword("connect")) {
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parse_connect();
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continue;
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}
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if (try_parse_keyword("wire")) {
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parse_wire();
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continue;
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}
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if (try_parse_keyword("cell")) {
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parse_cell();
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continue;
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}
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if (try_parse_keyword("memory")) {
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parse_memory();
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continue;
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}
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if (try_parse_keyword("process")) {
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parse_process();
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continue;
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}
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if (try_parse_keyword("end")) {
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expect_eol();
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break;
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}
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error("Unexpected token in module body: %s", error_token());
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}
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if (attrbuf.size() != 0)
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error("dangling attribute");
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current_module->fixup_ports();
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if (delete_current_module)
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delete current_module;
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else if (flag_lib)
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current_module->makeblackbox();
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current_module = nullptr;
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}
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void parse_attribute()
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{
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RTLIL::IdString id = parse_id();
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RTLIL::Const c = parse_const();
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attrbuf.insert({std::move(id), std::move(c)});
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expect_eol();
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}
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void parse_parameter()
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{
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RTLIL::IdString id = parse_id();
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current_module->avail_parameters(id);
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if (try_parse_eol())
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return;
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RTLIL::Const c = parse_const();
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current_module->parameter_default_values.insert({std::move(id), std::move(c)});
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expect_eol();
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}
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void parse_wire()
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{
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RTLIL::Wire *wire;
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int width = 1;
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int start_offset = 0;
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int port_id = 0;
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bool port_input = false;
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bool port_output = false;
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bool upto = false;
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bool is_signed = false;
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while (true)
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{
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (id.has_value()) {
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if (current_module->wire(*id) != nullptr)
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error("RTLIL error: redefinition of wire %s.", *id);
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wire = current_module->addWire(std::move(*id));
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break;
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}
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if (try_parse_keyword("width"))
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width = parse_integer();
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else if (try_parse_keyword("upto"))
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upto = true;
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else if (try_parse_keyword("signed"))
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is_signed = true;
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else if (try_parse_keyword("offset"))
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start_offset = parse_integer();
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else if (try_parse_keyword("input")) {
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port_id = parse_integer();
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port_input = true;
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} else if (try_parse_keyword("output")) {
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port_id = parse_integer();
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port_output = true;
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} else if (try_parse_keyword("inout")) {
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port_id = parse_integer();
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port_input = true;
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port_output = true;
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} else if (try_parse_eol())
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error("Missing wire ID");
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else
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error("Unexpected wire option: %s", error_token());
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}
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wire->attributes = std::move(attrbuf);
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wire->width = width;
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wire->upto = upto;
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wire->start_offset = start_offset;
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wire->is_signed = is_signed;
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wire->port_id = port_id;
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wire->port_input = port_input;
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wire->port_output = port_output;
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expect_eol();
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}
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void parse_memory()
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{
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RTLIL::Memory *memory = new RTLIL::Memory;
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memory->attributes = std::move(attrbuf);
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int width = 1;
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int start_offset = 0;
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int size = 0;
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while (true)
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{
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (id.has_value()) {
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if (current_module->memories.count(*id) != 0)
|
|
error("RTLIL error: redefinition of memory %s.", *id);
|
|
memory->name = std::move(*id);
|
|
break;
|
|
}
|
|
if (try_parse_keyword("width"))
|
|
width = parse_integer();
|
|
else if (try_parse_keyword("size"))
|
|
size = parse_integer();
|
|
else if (try_parse_keyword("offset"))
|
|
start_offset = parse_integer();
|
|
else if (try_parse_eol())
|
|
error("Missing memory ID");
|
|
else
|
|
error("Unexpected memory option: %s", error_token());
|
|
}
|
|
memory->width = width;
|
|
memory->start_offset = start_offset;
|
|
memory->size = size;
|
|
current_module->memories.insert({memory->name, memory});
|
|
expect_eol();
|
|
}
|
|
|
|
void parse_cell()
|
|
{
|
|
RTLIL::IdString cell_type = parse_id();
|
|
RTLIL::IdString cell_name = parse_id();
|
|
expect_eol();
|
|
|
|
if (current_module->cell(cell_name) != nullptr)
|
|
error("RTLIL error: redefinition of cell %s.", cell_name);
|
|
RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type);
|
|
cell->attributes = std::move(attrbuf);
|
|
|
|
while (true)
|
|
{
|
|
if (try_parse_keyword("parameter")) {
|
|
bool is_signed = false;
|
|
bool is_real = false;
|
|
if (try_parse_keyword("signed")) {
|
|
is_signed = true;
|
|
} else if (try_parse_keyword("real")) {
|
|
is_real = true;
|
|
}
|
|
RTLIL::IdString param_name = parse_id();
|
|
RTLIL::Const val = parse_const();
|
|
if (is_signed)
|
|
val.flags |= RTLIL::CONST_FLAG_SIGNED;
|
|
if (is_real)
|
|
val.flags |= RTLIL::CONST_FLAG_REAL;
|
|
cell->parameters.insert({std::move(param_name), std::move(val)});
|
|
expect_eol();
|
|
} else if (try_parse_keyword("connect")) {
|
|
RTLIL::IdString port_name = parse_id();
|
|
if (cell->hasPort(port_name))
|
|
error("RTLIL error: redefinition of cell port %s.", port_name);
|
|
cell->setPort(std::move(port_name), parse_sigspec());
|
|
expect_eol();
|
|
} else if (try_parse_keyword("end")) {
|
|
expect_eol();
|
|
break;
|
|
} else {
|
|
error("Unexpected token in cell body: %s", error_token());
|
|
}
|
|
}
|
|
}
|
|
|
|
void parse_connect()
|
|
{
|
|
if (attrbuf.size() != 0)
|
|
error("dangling attribute");
|
|
RTLIL::SigSpec s1 = parse_sigspec();
|
|
RTLIL::SigSpec s2 = parse_sigspec();
|
|
current_module->connect(std::move(s1), std::move(s2));
|
|
expect_eol();
|
|
}
|
|
|
|
void parse_case_body(RTLIL::CaseRule *current_case)
|
|
{
|
|
while (true)
|
|
{
|
|
if (try_parse_keyword("attribute"))
|
|
parse_attribute();
|
|
else if (try_parse_keyword("switch"))
|
|
parse_switch();
|
|
else if (try_parse_keyword("assign")) {
|
|
if (attrbuf.size() != 0)
|
|
error("dangling attribute");
|
|
// See https://github.com/YosysHQ/yosys/pull/4765 for discussion on this
|
|
// warning
|
|
if (!switch_stack.back()->empty())
|
|
warning("case rule assign statements after switch statements may cause unexpected behaviour. "
|
|
"The assign statement is reordered to come before all switch statements.");
|
|
RTLIL::SigSpec s1 = parse_sigspec();
|
|
RTLIL::SigSpec s2 = parse_sigspec();
|
|
current_case->actions.push_back(RTLIL::SigSig(std::move(s1), std::move(s2)));
|
|
expect_eol();
|
|
} else
|
|
return;
|
|
}
|
|
}
|
|
|
|
void parse_switch()
|
|
{
|
|
RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
|
|
rule->signal = parse_sigspec();
|
|
rule->attributes = std::move(attrbuf);
|
|
switch_stack.back()->push_back(rule);
|
|
expect_eol();
|
|
|
|
while (true) {
|
|
if (try_parse_keyword("attribute")) {
|
|
parse_attribute();
|
|
continue;
|
|
}
|
|
|
|
if (try_parse_keyword("end")) {
|
|
expect_eol();
|
|
break;
|
|
}
|
|
|
|
expect_keyword("case");
|
|
RTLIL::CaseRule *case_rule = new RTLIL::CaseRule;
|
|
case_rule->attributes = std::move(attrbuf);
|
|
rule->cases.push_back(case_rule);
|
|
switch_stack.push_back(&case_rule->switches);
|
|
case_stack.push_back(case_rule);
|
|
|
|
if (!try_parse_eol()) {
|
|
while (true) {
|
|
case_rule->compare.push_back(parse_sigspec());
|
|
if (try_parse_eol())
|
|
break;
|
|
expect_char(',');
|
|
}
|
|
}
|
|
|
|
parse_case_body(case_rule);
|
|
|
|
switch_stack.pop_back();
|
|
case_stack.pop_back();
|
|
}
|
|
}
|
|
|
|
void parse_process()
|
|
{
|
|
RTLIL::IdString proc_name = parse_id();
|
|
expect_eol();
|
|
|
|
if (current_module->processes.count(proc_name) != 0)
|
|
error("RTLIL error: redefinition of process %s.", proc_name);
|
|
RTLIL::Process *proc = current_module->addProcess(std::move(proc_name));
|
|
proc->attributes = std::move(attrbuf);
|
|
|
|
switch_stack.clear();
|
|
switch_stack.push_back(&proc->root_case.switches);
|
|
case_stack.clear();
|
|
case_stack.push_back(&proc->root_case);
|
|
|
|
parse_case_body(&proc->root_case);
|
|
|
|
while (try_parse_keyword("sync"))
|
|
{
|
|
RTLIL::SyncRule *rule = new RTLIL::SyncRule;
|
|
|
|
if (try_parse_keyword("low")) rule->type = RTLIL::ST0;
|
|
else if (try_parse_keyword("high")) rule->type = RTLIL::ST1;
|
|
else if (try_parse_keyword("posedge")) rule->type = RTLIL::STp;
|
|
else if (try_parse_keyword("negedge")) rule->type = RTLIL::STn;
|
|
else if (try_parse_keyword("edge")) rule->type = RTLIL::STe;
|
|
else if (try_parse_keyword("always")) rule->type = RTLIL::STa;
|
|
else if (try_parse_keyword("global")) rule->type = RTLIL::STg;
|
|
else if (try_parse_keyword("init")) rule->type = RTLIL::STi;
|
|
else error("Unexpected sync type: %s", error_token());
|
|
|
|
if (rule->type != RTLIL::STa && rule->type != RTLIL::STg && rule->type != RTLIL::STi)
|
|
rule->signal = parse_sigspec();
|
|
proc->syncs.push_back(rule);
|
|
expect_eol();
|
|
|
|
bool attributes_in_update_list = false;
|
|
while (true)
|
|
{
|
|
if (try_parse_keyword("update")) {
|
|
RTLIL::SigSpec s1 = parse_sigspec();
|
|
RTLIL::SigSpec s2 = parse_sigspec();
|
|
rule->actions.push_back(RTLIL::SigSig(std::move(s1), std::move(s2)));
|
|
expect_eol();
|
|
continue;
|
|
}
|
|
|
|
if (try_parse_keyword("attribute")) {
|
|
attributes_in_update_list = true;
|
|
parse_attribute();
|
|
continue;
|
|
}
|
|
|
|
if (!try_parse_keyword("memwr"))
|
|
break;
|
|
|
|
RTLIL::MemWriteAction act;
|
|
act.attributes = std::move(attrbuf);
|
|
act.memid = parse_id();
|
|
act.address = parse_sigspec();
|
|
act.data = parse_sigspec();
|
|
act.enable = parse_sigspec();
|
|
act.priority_mask = parse_const();
|
|
rule->mem_write_actions.push_back(std::move(act));
|
|
expect_eol();
|
|
}
|
|
// The old parser allowed dangling attributes before a "sync" to carry through
|
|
// the "sync", so we will too, for now.
|
|
if (attributes_in_update_list && attrbuf.size() > 0)
|
|
error("dangling attribute");
|
|
}
|
|
|
|
expect_keyword("end");
|
|
expect_eol();
|
|
}
|
|
|
|
RTLILFrontendWorker(RTLIL::Design *design) : design(design) {}
|
|
|
|
void parse(std::istream *f)
|
|
{
|
|
this->f = f;
|
|
line_num = 0;
|
|
advance_to_next_nonempty_line();
|
|
while (f->good())
|
|
{
|
|
if (try_parse_keyword("attribute")) {
|
|
parse_attribute();
|
|
continue;
|
|
}
|
|
if (try_parse_keyword("module")) {
|
|
parse_module();
|
|
continue;
|
|
}
|
|
if (try_parse_keyword("autoidx")) {
|
|
autoidx = std::max<int>(autoidx, parse_integer());
|
|
expect_eol();
|
|
continue;
|
|
}
|
|
error("Unexpected token: %s", error_token());
|
|
}
|
|
if (attrbuf.size() != 0)
|
|
error("dangling attribute");
|
|
}
|
|
};
|
|
|
|
struct RTLILFrontend : public Frontend {
|
|
RTLILFrontend() : Frontend("rtlil", "read modules from RTLIL file") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" read_rtlil [filename]\n");
|
|
log("\n");
|
|
log("Load modules from an RTLIL file to the current design. (RTLIL is a text\n");
|
|
log("representation of a design in yosys's internal format.)\n");
|
|
log("\n");
|
|
log(" -nooverwrite\n");
|
|
log(" ignore re-definitions of modules. (the default behavior is to\n");
|
|
log(" create an error message if the existing module is not a blackbox\n");
|
|
log(" module, and overwrite the existing module if it is a blackbox module.)\n");
|
|
log("\n");
|
|
log(" -overwrite\n");
|
|
log(" overwrite existing modules with the same name\n");
|
|
log("\n");
|
|
log(" -lib\n");
|
|
log(" only create empty blackbox modules\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
RTLILFrontendWorker worker(design);
|
|
|
|
log_header(design, "Executing RTLIL frontend.\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-nooverwrite") {
|
|
worker.flag_nooverwrite = true;
|
|
worker.flag_overwrite = false;
|
|
continue;
|
|
}
|
|
if (arg == "-overwrite") {
|
|
worker.flag_nooverwrite = false;
|
|
worker.flag_overwrite = true;
|
|
continue;
|
|
}
|
|
if (arg == "-lib") {
|
|
worker.flag_lib = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(f, filename, args, argidx);
|
|
|
|
log("Input filename: %s\n", filename);
|
|
|
|
worker.parse(f);
|
|
}
|
|
} RTLILFrontend;
|
|
|
|
YOSYS_NAMESPACE_END
|