mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
		
			
				
	
	
		
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			7 lines
		
	
	
	
		
			181 B
		
	
	
	
		
			Text
		
	
	
	
	
	
| read_verilog mulshift_test.v
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| hierarchy -check -top test
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| 
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| techmap -map sym_mul_map.v \
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|         -map mulshift_map.v;;
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| 
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| show -prefix mulshift -format dot -notitle -lib sym_mul_cells.v
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