mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
		
			
				
	
	
		
			4 lines
		
	
	
	
		
			90 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			4 lines
		
	
	
	
		
			90 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| module test(input [31:0]  a, b,
 | |
|             output [31:0] y);
 | |
| assign y = a + b;
 | |
| endmodule
 |